High- performanceand. Low- power. RISCArchitecture? Powerful. Instructions ? Most. Single. Clock. Cycle. Execution? General- purpose. Working. Registers? Up to 8 MIPSThroughput at 8 MHz? Dataand. Nonvolatile. Program. Memory? 8. K Bytes of In- System. Programmable. Flash. Endurance: 1,0. 00. Write/Erase. Cycles? Bytes of SRAM8- bit? Bytes of In- System. Programmable. EEPROMEndurance: 1. Write/Erase. Cycles. At90s8515 Datasheet Pdf 1n4001Microcontroller? Programming. Lockfor. Flash. Programand. EEPROMData. Security? Peripheral. Features? One. 8- bit. Timer/Counterwith. Separate. Prescalerwith 8. K Bytes? One. 16- bit.
Timer/Counterwith. Separate. Prescaler. Compare,Capture. Modesand. Dual. 8- ,9- , or 1. AT90S8515-8PC Mfg: ATMEL D/C: 07 Qty: 213 Adddate: 2009-12-3 9:00:18 SHENZHEN MGYTEK CO.,LTD. Contact: summer Tel: +86-755-83211108 Fax: +86-755-83211599 Select all Datasheet PDF Download Mfg: PDF NO.: Page Size: KB AT90S8515-8DC. Low-power, High-speed CMOS Process Technology? Fully Static Operation Power Consumption at 4 MHz, 3V, 25?C?? Power-down Mode: <1?A? 32 Programmable I/O Lines? AT90S8515 Ordering Information Speed (MHz) Power Supply Ordering Code Package Operation Range 4 2.7V - 6.0V AT90S8515-4AC 44A Commercial (0?C to 70?C) AT90S8515-4JC 44J AT90S8515-4PC 40P6 AT90S8515-4AI 44A Industrial (-40?C to 85?C) 44J. PWMIn- System? On- chip. Analog. Comparator? Programmable. Watchdog. Timerwith. On- chip. Oscillator. Programmable? Programmable. Serial. UART? Master/Slave SPI Serial. Interface. Flash? Special. Microcontroller. Features? Low- power. Idleand. Power- down. Modes? Externaland. Internal. Interrupt. Sources? Specifications. AT9. 0S8. 51. 5? Low- power,High- speed. CMOSProcess. Technology? Fully. Static. Operation. Power. Consumption at 4 MHz,3. V, 2. 5? C?? Idle. Mode: 1. 0 m. ASummary? Power- down. Mode: < 1 ? A? I/Oand. Packages? Programmable. I/OLines? PDIP,4. 4- lead PLCC and. TQFP? Operating. Voltages? Vfor. AT9. 0S8. 51. Vfor. AT9. 0S8. 51. Speed. Grades? 0 - 4 MHzfor. AT9. 0S8. 51. 5- 4? MHzfor. AT9. 0S8. Rev. 0. 84. 1GS? 0. Note: This is a summarydocument. A completedocument is. Pin Configurations. AT9. 0S8. 51. 52. GS? 0. 9/0. 1AT9. S8. 51. 5Description. The. AT9. 0S8. 51. CMOS8- bitmicrocontrollerbased on the. AVRRISCarchitecture. By executingpowerfulinstructions in a single clock cycle,the. AT9. 0S8. 51. 5achievesthroughputsapproaching 1 MIPSper. MHz,allowingthe system designer tooptimizepower consumption versus processing speed. Block. Diagram. Figure 1. The. AT9. 0S8. 51. Block Diagram. The. AVRcorecombines a richinstructionsetwith 3. Allthe 3. 2 registersaredirectlyconnected to the. Arithmetic. Logic. Unit(ALU),allowing two independent registers to be accessed in onesingleinstructionexecuted in. GS? 0. 9/0. 1oneclockcycle. Theresultingarchitecture is morecodeefficientwhileachievingthroughputs up to ten times fasterthanconventional. CISC microcontrollers. The. AT9. 0S8. 51. K bytes of In- System. Programmable. Flash,5. EEPROM,5. 12bytes. SRAM, 3. 2 general- purpose. I/Olines, 3. 2 general- purposeworkingregisters,flexibletimer/counterswithcomparemodes,internalandexternalinterrupts, a programmableserial. UART,programmable. Watchdog. Timerwithinternaloscillator, an SPIserialportandtwosoftware- selectablepower- saving modes. The. Idle. Modestopsthe. CPUwhileallowingthe. SRAM,timer/counters,SPIportandinterruptsystem to continuefunctioning. The. Power- downmode saves theregister con- tentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextexternalinterrupt or hardware reset. Thedevice is manufacturedusing. Atmel'shigh- densitynonvolatile memory technology. The. On- chip. In- System. Programmable. Flashallowstheprogrammemory to be repro- grammed. In- Systemthrough an SPIserialinterface or by a conventionalnonvolatilememory programmer. By combining an enhanced. RISC8- bit. CPUwith. In- System. Pro- g r a m m a b l e Flash on a monolithicchip,the. Atmel. AT9. 0S8. 51. The. AT9. 0S8. 51. AVR is supportedwith a fullsuite of programandsystemdevelopmenttoolsincluding: C compilers, macro assemblers, programdebugger/simulators, in- circuitemulators andevaluationkits. Pin Descriptions. VCCSupplyvoltage. GNDGround. Port A (PA7. PA0)Port A is an 8- bitbi- directional. I/Oport. Portpins can provideinternalpull- up resistors(selected foreachbit). The. Port A outputbuffers can sink 2. A andcandrive LED dis- playsdirectly. When pins. PA0 to PA7areused as inputsandareexternallypulledlow,theywill source current if theinternalpull- up resistors areactivated. The. Port A pinsaretri- statedwhen a reset condition becomes active,even if the clock is notactive. Port A serves as multiplexedaddress/datainput/outputwhenusingexternal. SRAM. Port B (PB7. PB0)Port B is an 8- bitbi- directional. I/Oportwithinternalpull- up resistors. The. Port B outputbufferscansink 2. A. As inputs,Port B pinsthatareexternallypulledlowwill sourcecurrent if thepull- up resistors areactivated. The. Port B pinsaretri- statedwhen a resetcondition becomes active,even if the clock is notactive. Port B also serves thefunctions of variousspecialfeatures of the. AT9. 0S8. 51. 5 as listedon page. Port C (PC7. PC0)Port C is an 8- bitbi- directional. I/Oportwithinternalpull- up resistors. The. Port C outputbufferscansink 2. A. As inputs,Port C pinsthatareexternallypulledlowwill sourcecurrent if thepull- up resistors areactivated. The. Port C pinsaretri- statedwhen a resetcondition becomes active,even if the clock is notactive. Port C also serves as address outputwhenusingexternal. SRAM. Port D (PD7. PD0)Port D is an 8- bitbi- directional. I/Oportwithinternalpull- up resistors. The. Port D outputbuffers can sink 2. A. As inputs,Port D pinsthatareexternallypulledlowwill source. AT9. 0S8. 51. 54. GS? 0. 9/0. 1AT9. S8. 51. 5current if thepull- up resistors areactivated. The. Port D pinsaretri- statedwhen a resetcondition becomes active,even if the clock is notactive. Port D also serves thefunctions of variousspecialfeatures of the. AT9. 0S8. 51. 5 as listedon page. Reset input. A lowlevel on thispinfor more than 5. RESETclock is notrunning. Shorter pulses arenotguaranteed to generate a reset. XTAL1. Input to theinvertingoscillatoramplifierandinput to theinternal clock operating circuit. XTAL2. Output from theinvertingoscillatoramplifier. ICPICP is theinputpinforthe. Timer/Counter. 1Input. Capturefunction. OC1. BOC1. B is theoutputpinforthe. Timer/Counter. 1Output Compare. B function. ALEALE is the. Address. Latch. Enableusedwhenthe. External. Memory is enabled. The. ALEstrobe is used to latchthelow- order address (8 bits) into an address latchduringthe firstaccess cycle, andthe. AD0 - 7 pinsareusedfordataduringthe second access cycle. GS? 0. 9/0. 1Register Summary. Address. Name. Bit 7. Bit 6. Bit 5. Bit 4. Bit 3. Bit 2. Bit 1. Bit 0. Page$3. F ($5. F)SREGITHSVNZCpage 2. E($5. E)SPHSP1. 5SP1. SP1. 3SP1. 2SP1. 1SP1. SP9. SP8page 2. 1$3. D ($5. D)SPLSP7. SP6. SP5. SP4. SP3. SP2. SP1. SP0page 2. 1$3. C ($5. C)Reserved$3. B($5. B)GIMSKINT1. INT0- -- -- -page 2. A($5. A)GIFRINTF1. INTF0page 2. 6$3. TIMSKTOIE1. OCIE1. AOCIE1. B- TICIE1- TOIE0- page 2. TIFRTOV1. OCF1. AOCF1. B- ICF1- TOV0- page 2. Reserved$3. 6 ($5. Reserved$3. 5 ($5. MCUCRSRESRWSESMISC1. ISC1. 0ISC0. 1ISC0. Reserved$3. 3 ($5. TCCR0- -- -- CS0. CS0. 1CS0. 0page 3. TCNT0. Timer/Counter. Bits)page 3. 4.. Reserved$2. F ($4. F)TCCR1. ACOM1. A1. COM1. A0. COM1. B1. COM1. B0- -PWM1. PWM1. 0page 3. 5$2. E($4. E)TCCR1. BICNC1. ICES1- -CTC1. CS1. CS1. 1CS1. 0page 3. D ($4. D)TCNT1. HTimer/Counter. Counter Register. High Bytepage 3. 8$2. C ($4. C)TCNT1. LTimer/Counter. Counter Register. Low Bytepage 3. 8$2. B($4. B)OCR1. AHTimer/Counter. Output Compare Register A High Bytepage 3. A($4. A)OCR1. ALTimer/Counter. Output Compare Register A Low Bytepage 3. OCR1. BHTimer/Counter. Output Compare Register B High Bytepage 3. OCR1. BLTimer/Counter. Output Compare Register B Low Bytepage 3. Reserved$2. 5 ($4. ICR1. HTimer/Counter. Input Capture Register. High Bytepage 3. 9$2. ICR1. LTimer/Counter. Input Capture Register. Low Bytepage 3. 9.. Reserved$2. 1 ($4. WDTCR- -- WDTOEWDEWDP2. WDP1. WDP0page 4. Reserved$1. F ($3. F)EEARH- -- -- -- EEAR8page 4. E($3. E)EEARLEEPROM Address. Register. Low Bytepage 4. D ($3. D)EEDREEPROM Data Registerpage 4. C ($3. C)EECR- -- -- EEMWEEEWEEEREpage 4. B($3. B)PORTAPORTA7. PORTA6. PORTA5. PORTA4. PORTA3. PORTA2. PORTA1. PORTA0page 6. 3$1. A($3. A)DDRADDA7. DDA6. DDA5. DDA4. DDA3. DDA2. DDA1. DDA0page 6. 3$1. 9 ($3. PINAPINA7. PINA6. PINA5. PINA4. PINA3. PINA2. PINA1. PINA0page 6. PORTBPORTB7. PORTB6. PORTB5. PORTB4. PORTB3. PORTB2. PORTB1. PORTB0page 6. DDRBDDB7. DDB6. DDB5. DDB4. DDB3. DDB2. DDB1. DDB0page 6. PINBPINB7. PINB6. PINB5. PINB4. PINB3. PINB2. PINB1. PINB0page 6. PORTCPORTC7. PORTC6. PORTC5. PORTC4. PORTC3. PORTC2. PORTC1. PORTC0page 7. DDRCDDC7. DDC6. DDC5. DDC4. DDC3. DDC2. DDC1. DDC0page 7. PINCPINC7. PINC6. PINC5. PINC4. PINC3. PINC2. PINC1. PINC0page 7. PORTDPORTD7. PORTD6. PORTD5. PORTD4. PORTD3. PORTD2. PORTD1. PORTD0page 7. DDRDDDD7. DDD6. DDD5. DDD4. DDD3. DDD2. DDD1. DDD0page 7. PINDPIND7. PIND6. PIND5. PIND4. PIND3. PIND2. PIND1. PIND0page 7. F ($2. F)SPDRSPI Data Registerpage 5. E($2. E)SPSRSPIFWCOL- -- -- -page 5. D ($2. D)SPCRSPIESPEDORDMSTRCPOLCPHASPR1. SPR0page 4. 9$0. C ($2. C)UDRUART I/O Data Registerpage 5. B($2. B)USRRXCTXCUDREFEOR- -- page 5. A($2. A)UCRRXCIETXCIEUDRIERXENTXENCHR9. RXB8. TXB8page 5. UBRRUARTBaud Rate Registerpage 5. ACSRACD- ACOACIACIEACICACIS1. ACIS0page 5. 9.. Reserved$0. Reserved. Notes: 1. Forcompatibility with futuredevices,reservedbitsshould be written to zero if accessed. Reserved I/O memoryaddressesshouldnever be written. Some of thestatusflagsarecleared by writing a logical? Rr. ANDRd, Rr. Logical. ANDRegisters. Z,N,V1. Rd ? Rd. TSTRd. Test for Zero or Minus. Z,N,V1. Rd . A0. 4/1. AT9. 0S8. 51. 51. GS? 0. 9/0. 1AT9. S8. 51. 54. 4J4. 4J,4. Plastic. J- leaded. Chip Carrier (PLCC)Dimensions in Milimeters and (Inches)*JEDECSTANDARDMS- 0. AC1. 1. 4(0. 0. 45) X 4. PINNO. 1. 1. 1. 4(0. X 4. 5? 0. 3. 18(0. IDENTIFY0. 1. 91(0. SQ1. 6. 7. 0(0. 6. SQ1. 6. 5. 0(0. 6. SQ1. 7. 4. 0(0. 6. TYP0. 5. 0(0. 0. 20)MIN1. REF SQ2. 1. 1(0. 0. MAX 4. 5? MAX(3. X)*Controlling dimensions: Inches. REV. A0. 4/1. 1/2. GS? 0. 9/0. 14. 0P6. Plastic. Dual Inline. Parkage (PDIP), 0. A0. 4/1. 1/2. 00. AT9. 0S8. 51. 51. GS? 0. 9/0. 1Atmel. Headquarters. Atmel. Product. Operations. Corporate. Headquarters. Atmel. Colorado. Springs. Orchard Parkway. 11. E. Cheyenne Mtn. Blvd. San Jose, CA 9. 51. Colorado Springs, CO 8. TEL (4. 08) 4. 41- 0. TEL (7. 19) 5. 76- 3. FAX (4. 08) 4. 87- 2. FAX (7. 19) 5. 40- 1. Europe. Atmel. Grenoble. Atmel Sar. LAvenue de Rochepleine. Route des Arsenaux 4. BP 1. 23. Casa Postale 8. Saint- Egreve. Cedex, France. CH- 1. 70. 5 Fribourg. TEL (3. 3) 4- 7. 65. Switzerland. FAX (3. TEL(4. 1) 2. 6- 4. Atmel. Heilbronn. FAX(4. 1) 2. 6- 4. Theresienstrasse 2. Asia. POB3. 53. 5Atmel.
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